1. Field of the Invention
This invention relates to electrical testing methods, and more particularly to a method and apparatus for testing both the electrical devices and circuit connections of a printed circuit board.
2. Description of the Prior Art
Printed circuit boards are coming into evermore popular use for packaging complex electronic circuits. Such boards today may have many hundreds of electrical devices, including integrated circuit packages or chips which themselves take the place of numerous discrete devices, and thousands of circuit interconnections. Formulating testing procedures to ensure that each of the devices and circuit connections work properly, both by themselves and together on the board, has accordingly become quite important. The ideal testing technique should be able to test all of the board components under the operating conditions they may be expected to encounter, should identify and isolate any defects in either the electrical devices mounted on the board or the connections between such devices, should be efficient in terms of both preparation and operating time, and should be capable of readily accomodating to changes in board design.
Perhaps the most accurate method in use today for testing printed circuit boards involves digital logic simulation. In this technique the logic components or devices, as well as the board topology or network structure, are modeled by a computer program. A programmed set of logic stimuli is then applied to the board model to generate a response which can be used as a reference in testing actual boards. The test program is designed for the specific board to be tested in accordance with known techniques, such as NTS MAINCO programming language.
Digital logic simulation is a very precise technique in that it provides expected response values for all logic nodes on the board, both output nodes at the edge of the board and internal nodes. Defects on a test board can be detected and located with high accuracy, since the expected logic state of each response node can be known for each step of the test program, and compared with the actual output states exhibited by a test board when a test program is run on it. On the other hand, this technique requires the expenditure of a considerable amount of time to both prepare the model and in the actual testing of the boards, and the model must be very accurate in order to achieve good results. Also, while the simulation may be valid, the test program itself may be inadequate to locate some possible defects. The time factor is particularly important when a final board design has not been reached. If the board is subsequently changed the model must also be changed, and this is again a time consuming process. The simulation technique is therefor best adapted to situations in which the final system design has been reached.
Other testing techniques are known which are faster than logic simulation, but which do not produce as much useful information. For example, a test program may be applied to a test board, and the resulting logic pattern at the board output nodes compared with the corresponding pattern for a reference board. With this technique defects on a board may be detected, but they can be quite difficult to isolate. Also, a board defect may exist but not become manifest if it has only a transitory effect during the application of a test program, or if it is cancelled by other defects on the board. In either case, the final test response after the program has run may correspond to the reference response, thereby producing a false indication that the board is operating properly.
Another technique involves the acquisition of transition counts for all or selected output nodes on a test board, and the comparison of these counts with a reference. According to the transition count method, a count is accumulated for selected output nodes as the test program is applied to the board, and a number is added to the count for each output node every time the node shifts from one logic state to the other, or every time a node is sampled. The number added may be either a constant or a known variable, depending upon whether the basic method or a variation thereof is selected.
Several variations of this technique have been developed to reduce the chance of multiple board defects cancelling each other and giving a correct final transition count as a result of incorrect board operation. According to one variation, the original transition count is modified by adding some other number to the basic transition count each time the output node logic state changes. For example, the order of the test program step at which the logic transition occurs may be added to the basic transition number. Thus, if a transition from a "0" to a "1" logic state is indicated by the base transition number 1, that transition on the 178th step of the test program will advance the accumulated transition count by a total of 179.
Another variation on the transition count technique, known as cyclic redundancy code, makes use of a mathematical algorithm to detect output errors over a long sequence of serial data by generating numbers which are unique to the sequence of transitions at the output nodes, rather than being determined solely by the accumulated transition counts. This technique is highly accurate in detecting any deviations from the expected sequence of logic transitions, but like its related transition counting techniques it gives little or no information as to the exact problem which might be causing a divergence between the expected and actual logic sequence at a particular output node.
In a further method known to the art, the individual devices mounted on the board are simply tested one at a time by applying a set of input stimuli to each device, and testing to see if it produces the correct output. While this technique is effective in identifying and isolating particular device problems, it requires the time consuming procedure of placing an integrated circuit probe or clip on every one of the board devices and testing the devices individually. This problem may become prohibitive in the case of large circuit boards, such as those used in high-capacity computer systems. Also, while the operation of each device individually may be ascertained, the board as a whole is untested, and faulty operation due to bad connections or short circuits external to the individual devices may go undetected.
For each of the testing techniques described above, it is assumed that an adequate test program is available to exercise the circuit boards in a proper manner such that any defects on the boards will become manifest by comparing the board response to a reference. In some cases, however, the test program may not exercise the board sufficiently, and certain board defects may pass unnoticed. There is therefor a need for ensuring that a test program intended to be used with a particular board design is indeed adequate for that board.